Simulated Tempering for VLSI Floorplan Designs

In the past two decades, the simulated annealing technique has been considered as a powerful approach to handle many NP-hard optimization problems in VLSI designs. Recently, a new Monte Carlo and optimization technique, named simulated tempering, was invented and has been successfully applied to many scientific problems, from random field Ising modeling to the traveling salesman problem. It is designed to overcome the drawback in simulated annealing when the problem has a rough energy landscape with many local minima separated by high energy barriers. In this paper, we have successfully applied simulated tempering to slicing floorplan design with consideration of both area and wirelength optimization. Very promising experimental results were obtained. This is the first work adopting simulated tempering technique for solving optimization problems in the VLSI CAD field. We expect to see more applications of this technique to other VLSI design problems.